1. Field of the Invention
The embodiments disclosed herein relate to modeling parasitic resistances in integrated circuits and, more particularly, to embodiments of a method, a system and a program storage device for modeling the total contact resistance (Rtot) of a contact bar that electrically connects a plurality of semiconductor fins to an additional interconnect structure (e.g., another contact bar, a via or a via bar).
2. Description of the Related Art
Parasitic contact resistance is one of the larger parasitic resistances that will impact the performance of very large scale integration (VLSI) circuits, such as ring oscillators, logic gates (e.g., NAND gates, NOR gates, etc.), etc. Thus, during integrated circuit design, accurate modeling of the total resistance (Rtot) of contacts and contact bars is very important. Currently, the total resistance of a contact bar, which traverses and is electrically connected to a diffusion region of a planar field effect transistor (FET) or is electrically connected to multiple semiconductor fins of a multi-gate field effect transistor (MUGFET), is determined using an electromagnetic field solver (i.e., an electromagnetic solver), which outputs a numerical value for the total resistance. However, in compact models, a closed-form expression for the total resistance of each contact bar is required, as opposed to a numerical value. Therefore, there is a need in the art for an improved method for accurately modeling the total resistance of a contact bar using a closed-form expression.